The present invention relates to programming of non-volatile memory devices and, more particularly, to a method of operating a non-volatile memory device, in which pass voltages can be set according to program speeds.
There is an increasing demand for non-volatile memory devices that can be electrically programmed and erased and retain data even when power is not supplied. Further, high-integrated technologies of memory cells have been developed in order to develop large-capacity memory devices that are able to store large amounts of data. To this end, a NAND type flash memory device in which a plurality of memory cells is connected in series to form one string and a plurality of strings constitutes one memory cell array was proposed.
In general, a flash memory cell includes a gate in which a tunnel insulating layer, a floating gate, a dielectric layer and a control gate are stacked over a semiconductor substrate, and junctions formed in the semiconductor substrate on both sides of the gate. The flash memory cell is programmed as hot electrons are injected into the floating gate and erased as injected electrons are discharged by Fowler-Nordheim (F-N) tunneling.
FIG. 1A is a view showing the unit string of a flash memory device.
Referring to FIG. 1A, the unit string of a NAND flash memory device includes memory cells MC0, . . . , MC31 connected in series between a drain select transistor DST for selecting a unit string and a source select transistor SST for selecting ground. Each memory cell has a gate in which a floating gate and a control gate are stacked.
The string is connected to a bit line BL. A plurality of structures to which the string and the bit line are connected is connected in parallel to thereby form one block. The blocks are symmetrically arranged on the basis of a bit line contact. The select transistors DST, SST and the memory cells MC0, . . . , MC31 are arranged in matrix form of rows and columns. The gates of the drain select transistor DST and the source select transistor SST arranged in the same column are connected to a drain select line DSL and a source select line SSL, respectively. The gates of the memory cells MC0, . . . , MC31 arranged in the same column are also connected to a plurality of corresponding word lines WL0, . . . , WL31. Further, the drain of the drain select transistor DST is connected to the bit line BL and to the source of the source select transistor SST is connected a common source line CSL.
A program operation of the NAND flash memory device as constructed above is described below.
A program operation is performed by applying 0V to a selected bit line and a program voltage Vpgm to a selected word line such that electrons of a channel area are injected into the floating gate by Fowler-Nordheim (F-N) tunneling, which is generated due to a high voltage difference between the channel area and the control gate of a selected memory cell.
However, the program voltage Vpgm is applied to not only a selected memory cell, but also to unselected memory cells arranged along the same word line, so that the unselected memory cells connected to the same word line are also programmed. This phenomenon is called program disturbance. In order to prevent such program disturbance, a channel voltage Vch of memory cells belonging to the same string is boosted to thereby prevent unselected memory cells from being programmed in such a manner that the source of the drain select transistor DST of a string, including unselected memory cells connected to a selected word line and unselected bit lines, is charged to a level (Vcc-Vth) (where Vcc is a power source voltage and Vth is the threshold voltage of the drain select transistor). The program voltage Vpgm is applied to the selected word, and a pass voltage Vpass is applied to the unselected word lines.
In other words, as shown in FIG. 1A, when the thirtieth word line is selected, if the program voltage Vpgm is applied to the thirtieth word line WL29, the pass voltage Vpass is applied to the remaining word lines, and the drain select transistor DST and the source select transistor SST are turned off, channel boosting is generated. Thus, a channel voltage is raised with a channel being formed, as shown in FIG. 1A, so that unselected memory cells can be prevented from being programmed. To this end, it is necessary to effectively perform channel boosting.
Further, when the number of programmed cells among memory cells constituting a string is many, channel boosting is decreased. To prevent this problem, the following word line voltages can be provided.
FIG. 1B is a view illustrating the supply of voltages to word lines according to an erase area self-boosting (EASB) method of the flash memory device.
FIG. 1B illustrates an EASB method for preventing boosting of programmed cells. In order to implement program inhibition, the twenty-ninth word line WL28, that is, a word line on the SSL line side of the thirtieth word line WL29 for program is turned off in order to form a low channel boosting area between the first word line WL0 and the thirtieth word line WL29 and a high channel boosting area between the thirtieth word line WL29 and the thirty-second word line WL31.
FIG. 1C is a partial enlarged view of FIG. 1B.
FIG. 1C shows an enlarged view of an area 110 of FIG. 1B. As shown in FIG. 1C, as a gate induced drain leakage (GIDL) phenomenon is generated when high channel boosting is generated, the number of electrons created can be increased, and disturbance failure due to hot electrons, which are generated by a strong electronic field caused by a high potential difference, may occur.
FIG. 2 is a graph showing the relationship between a channel boosting level and program disturbance.
From FIG. 2, it can be seen that, when a channel boosting level is low, program disturbance due to F-N tunneling can be generated and, when a channel boosting level is high, program disturbance due to hot electron injection can be generated. Accordingly, there is a need for a method of controlling the pass voltage Vpass applied to the word lines for improved channel boosting.